Aphcity/suyu
1
0
Fork 0
forked from suyu/suyu
Code Pull requests Activity Actions

Fix BLX LR opcode interpretation

Browse source
This commit is contained in:
mailwl 2016-04-09 06:46:03 +03:00
parent a4c5d8fd50
commit 2efc1c9348
1 changed files with 3 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
View file

@ -4080,11 +4080,12 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
unsigned int inst = inst_cream->inst; unsigned int inst = inst_cream->inst;
if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) { if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) {
const u32 jump_address = cpu->Reg[inst_cream->val.Rm];
cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize()); cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
if(cpu->TFlag) if(cpu->TFlag)
cpu->Reg[14] |= 0x1; cpu->Reg[14] |= 0x1;
cpu->Reg[15] = cpu->Reg[inst_cream->val.Rm] & 0xfffffffe; cpu->Reg[15] = jump_address & 0xfffffffe;
cpu->TFlag = cpu->Reg[inst_cream->val.Rm] & 0x1; cpu->TFlag = jump_address & 0x1;
} else { } else {
cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize()); cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
cpu->TFlag = 0x1; cpu->TFlag = 0x1;