Shader_IR: Implement FLO instruction.
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parent
95137a04e1
commit
f3d1b370aa
5 changed files with 35 additions and 0 deletions
src/video_core
engines
renderer_opengl
renderer_vulkan
shader
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@ -799,6 +799,12 @@ union Instruction {
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BitField<40, 1, u64> invert;
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} popc;
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union {
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BitField<41, 1, u64> sh;
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BitField<40, 1, u64> invert;
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BitField<48, 1, u64> is_signed;
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} flo;
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union {
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BitField<39, 3, u64> pred;
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BitField<42, 1, u64> neg_pred;
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@ -1472,6 +1472,11 @@ private:
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return GenerateUnary(operation, "bitCount", type, type);
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}
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template <Type type>
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Expression BitMSB(Operation operation) {
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return GenerateUnary(operation, "findMSB", type, type);
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}
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Expression HNegate(Operation operation) {
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const auto GetNegate = [&](std::size_t index) {
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return VisitOperand(operation, index).AsBool() + " ? -1 : 1";
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@ -2043,6 +2048,7 @@ private:
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&GLSLDecompiler::BitfieldInsert<Type::Int>,
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&GLSLDecompiler::BitfieldExtract<Type::Int>,
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&GLSLDecompiler::BitCount<Type::Int>,
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&GLSLDecompiler::BitMSB<Type::Int>,
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&GLSLDecompiler::Add<Type::Uint>,
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&GLSLDecompiler::Mul<Type::Uint>,
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@ -2061,6 +2067,7 @@ private:
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&GLSLDecompiler::BitfieldInsert<Type::Uint>,
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&GLSLDecompiler::BitfieldExtract<Type::Uint>,
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&GLSLDecompiler::BitCount<Type::Uint>,
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&GLSLDecompiler::BitMSB<Type::Uint>,
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&GLSLDecompiler::Add<Type::HalfFloat>,
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&GLSLDecompiler::Mul<Type::HalfFloat>,
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@ -1390,6 +1390,7 @@ private:
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&SPIRVDecompiler::Quaternary<&Module::OpBitFieldInsert, Type::Int>,
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&SPIRVDecompiler::Ternary<&Module::OpBitFieldSExtract, Type::Int>,
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&SPIRVDecompiler::Unary<&Module::OpBitCount, Type::Int>,
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&SPIRVDecompiler::Unary<&Module::OpFindSMsb, Type::Int>,
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&SPIRVDecompiler::Binary<&Module::OpIAdd, Type::Uint>,
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&SPIRVDecompiler::Binary<&Module::OpIMul, Type::Uint>,
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@ -1408,6 +1409,7 @@ private:
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&SPIRVDecompiler::Quaternary<&Module::OpBitFieldInsert, Type::Uint>,
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&SPIRVDecompiler::Ternary<&Module::OpBitFieldUExtract, Type::Uint>,
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&SPIRVDecompiler::Unary<&Module::OpBitCount, Type::Uint>,
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&SPIRVDecompiler::Unary<&Module::OpFindUMsb, Type::Uint>,
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&SPIRVDecompiler::Binary<&Module::OpFAdd, Type::HalfFloat>,
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&SPIRVDecompiler::Binary<&Module::OpFMul, Type::HalfFloat>,
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@ -130,6 +130,24 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) {
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::FLO_R:
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case OpCode::Id::FLO_C:
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case OpCode::Id::FLO_IMM: {
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Node value;
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if (instr.flo.invert) {
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op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b);
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}
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if (instr.flo.is_signed) {
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value = Operation(OperationCode::IBitMSB, NO_PRECISE, op_b);
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} else {
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value = Operation(OperationCode::UBitMSB, NO_PRECISE, op_b);
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}
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if (instr.flo.sh) {
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value = Operation(OperationCode::UBitwiseXor, NO_PRECISE, value, Immediate(31));
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}
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::SEL_C:
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case OpCode::Id::SEL_R:
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case OpCode::Id::SEL_IMM: {
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@ -68,6 +68,7 @@ enum class OperationCode {
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IBitfieldInsert, /// (MetaArithmetic, int base, int insert, int offset, int bits) -> int
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IBitfieldExtract, /// (MetaArithmetic, int value, int offset, int offset) -> int
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IBitCount, /// (MetaArithmetic, int) -> int
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IBitMSB, /// (MetaArithmetic, int) -> int
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UAdd, /// (MetaArithmetic, uint a, uint b) -> uint
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UMul, /// (MetaArithmetic, uint a, uint b) -> uint
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@ -86,6 +87,7 @@ enum class OperationCode {
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UBitfieldInsert, /// (MetaArithmetic, uint base, uint insert, int offset, int bits) -> uint
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UBitfieldExtract, /// (MetaArithmetic, uint value, int offset, int offset) -> uint
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UBitCount, /// (MetaArithmetic, uint) -> uint
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UBitMSB, /// (MetaArithmetic, uint) -> uint
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HAdd, /// (MetaArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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HMul, /// (MetaArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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